Integrated circuit layout (aka IC layout, IC mark layout) refers to the manifestation of an integrated circuit concerning geometric shapes related to the patterns of oxide, metal, or semiconductor layers that constitute the components of the IC. Previously, the overall process was referred to as a “tape out” as preceding ICs leveraged graphical black crepe tape on mylar media.
When utilizing a standard process-where the connection of various thermal, chemical, and photographic variables is accessible and aptly controlled-the behaviour of the finished IC depends on the positions and interactions of the geometric shapes. With a computer-based layout tool, the layout technician or engineer carefully positioned and connects available components that constituent the chip in a way that fulfils underlying conditions concerning size, performance, density, and manufacturability. This method is subdivided between two fundamental layout disciplines- Digital and Analog
Tests Performed On the Integrated Circuit Layout
The generated layout should undergo various quality checks during physical vetting. The common checks include:
Design Rule Checking
Design Rule Checking (DRC) ensures whether the design fulfills the constraints of the process technology that deals with its manufacturing. DRC checking serves as an imperative part of the physical design flow and affirms the design fulfills manufacturing requisites. The process technology conditions are underpinned by process engineers & fabrication units.
Layout versus Schematic (LVS)
Layout Versus Schematic compares the extracted netlist to the fundamental schematic netlist to check if they match. The comparison check is deemed a success if the concerned devices and nerts match the device & the nets of the layout. The device properties can undergo comparison to check whether they match within a given tolerance. During properties comparison, all the properties should match thoroughly to accomplish a clean comparison.
In the context of electronic design automation, parasitic extraction refers to the estimation of the parasitic effects in the designed devices and underlying wiring interconnects -parasitic capacitances, parasitic inductances, and parasitic resistances known as parasitic components or simply parasitic.
Parasitic extraction aims to create a legitimate analog model of the circuit so that simulations can emulate actual analog & digital circuit responses.
Antenna Rule Checking
Antenna rules refer to a typical name for rules that verify the ratio of material’s amount in two layers from the same node. Their utilization limits the damage of the thin gate oxide while production because of charge gathering on interconnect layers in certain fabrication steps.
Electrical Rule Checking
Electrical rule checking determines the potential of the schematic, affirming that circuits will function as designed. ERC violations may lead to compromised yield and/or circuit outage or electrical malfunction post-product delivery.
Role of Layout Post-Processing and Data Translation in Integrated Circuit Layout
When the vetting process comes to an end, layout post-processing comes into effect where the data translation takes place in industry-recognized format-GDSII and is sent to the foundry.
The process of data transfer to the foundry refers to as takeout. The foundry transforms this data into mask data and utilizes it to produce the photomasks, which are used in the photolithographic process. On the previous day, the IC design layout was manually created via films and opaque tapes, a development derived from the preceding days of PCB design-tape out.
Modern IC layout is achieved via IC layout editor software, largely automatically via EDA tools, including route tools or schematic-driven layout tools. Generally this comprises a library of standard cells.
Different Legislations Governing the Integrated Circuit Layout/Design
An integrated circuit (IC) layout refers to a 3-D schematic of the components & interconnections constituting the IC. An integrated circuit is nothing but an electronic circuit comparison of different circuit parts integrated into some media and acts as an individual unit.
A solid semiconductor is being utilized as the medium. The circuit may be integrated into a small piece of silicon for the production process. Since all commercial ICs are manufactured from semiconductors, primarily silicon, the terms Silicon Chip and Semiconductor have been utilized interchangeably with IC.
Many devices leverage ICs, including a digital clocks, smart TVs, PCs, and so on. The legislations like the Semiconductor Integrated Circuits Layout-Design Rules of 2001 and the Semiconductor Integrated Circuits Layout-Design Act of 2000 ensure legal protection for the original layout design. This prevents others from imitating the integrated circuit layout, helping firms to overcome fiscal losses.
Status of Integrated Circuit Layout Designs in India
Though India has adhered to the TRIPS agreement concerning the protection of semiconductor IC and layout design and approved the act, the lack of implementation still exists owing to the low awareness level among the people.
There is a common misconception among Indian industries that patents can be used to protect the integrated circuit layout. A patent is all about the invention, whereas a copyright secures the artistic, cinematographic, and literary composition. Thus, the mere modification of the design cannot qualify for patent registration. Integrated circuit layout falls somewhere around the intersection of patent and design registration.
Intellectual property protection for Integrated Circuit layout plays a vital role globally in ensuring a level playing field. Unfortunately, no legislation in India specifically deals with software protection. Considering the prevailing growth rate and technological advancement in India, the government, in association with concerned committees, must stride forward to underpin extensive legislation for Integrated circuit layout/design.
Read Our Article: Patent in India: Registration and Filing Process